HEATKEYS

TimingTool diagram editor is free to use online. TimingTool application generates VHDL or Verilog test benches from timing diagrams.

TimeGen is a timing diagram software editor that allows engineers to easily create design specifications and timing diagrams.

SynaptiCAD: EDA supplier for timing diagram editors, simulators, and VHDL and Verilog debug tools.

SourceForge.net. Fast, secure and free downloads from the largest Open Source applications and software directory

FPGA - Actel

This is an electronics forum where you can talk about anything related to circuit building, electronic projects and electrical repairs.

A discussion forum for electronics and circuits

review from Velocity Reviews

UML design and business analysis tool for modeling, documenting, reverse engineering, building and maintaining object-oriented software systems, fast and intuitive. Great features, great price.